Nonvolatile memory device with multiple references and corresponding control method

ABSTRACT

A memory device includes a group of memory cells organized in rows and columns and a first addressing circuit for addressing said memory cells of said group on the basis of a cell address. The device further includes a plurality of sets of reference cells, associated to the group, each of said set having a plurality of reference cells, and a second addressing circuit for addressing one of the reference cells during operations of read and verify of addressed memory cells.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a nonvolatile memory device withmultiple references and to a control method thereof.

2. Description of the Related Art

It is known that reading nonvolatile memory cells, for example of anEEPROM or Flash type, may cause undesirable phenomena of spuriousprogramming (referred to also as “read disturb”). With reference to FIG.1, a nonvolatile memory cell 1 comprises: a source region 2 and a drainregion 3, both formed in a semiconductor substrate 4 and respectivelyprovided with a source terminal 1 a and a drain terminal 1 b; a channelregion 5, extending in the substrate 4 between the source region 2 andthe drain region 3; a floating-gate region 6, separated from the channelregion 5 by a tunnel-oxide layer 7; and a control-gate region 8, whichis in turn separated from the floating-gate region 6 by an insulatinglayer 9 and is provided with a gate terminal 1 c. During read or verifyoperations, an electric field E is set up between the floating-gateregion 6 and the substrate 4 (in particular, the channel region 5). Saidelectric field E is necessary to enable passage of current between thesource region 2 and the drain region 3. However, a mechanism altogethersimilar to that of programming causes a fraction of the electronstraveling in the channel region 5 to be deviated and trapped in thefloating-gate region 6, thus altering the threshold voltage of the cell1. The phenomenon of spurious programming is all the more effective thelower the threshold voltage of the cell 1 (since the electric field E isgreater) and regards above all the cells used as reference for the readoperations, program-verify operations, erase-verify operations, anddepletion-verify operations. In fact, whereas the array cells arerandomly selected for reading/programming, the reference cells aresystematically used at every access to the memory. Consequently, thereference cells are read a number of times that is greater by someorders of magnitude than the average number of accesses to theindividual array cell.

In practice, two harmful effects occur. The first, illustrated in FIGS.2 a and 2 b in the case of a four-level (two-bit) cell, regards thereduction in the distance that separates the ranges of thresholdvoltages associated to the various levels (designated by V_(T1), V_(T2),V_(T3) and V_(T4)) and between the references (the read references, theprogram-verify references, the erase-verify reference, and thedepletion-verify reference, are designated, respectively, by V_(R1),V_(R2), V_(R3), by V_(P1), V_(P2), V_(P3), by V_(E), and by V_(D)). Infact, the cells having a lower threshold voltage are subject to a moreintense drift, due to spurious programming, and hence, with time, thereference ranges and levels tend to be compressed (FIG. 2 b) as comparedto an initial situation (FIG. 2 a). The number of reading errorsconsequently tends to increase, even following upon modest disturbance.

The second effect, which is more serious, depends upon the higherreading frequency of the reference cells and is illustrated in FIGS. 2 aand 2 c. The drift in the threshold voltages of the reference cells, infact, is faster as compared to that of the array cells. Consequently,with respect to the initial situation of FIG. 2 a, the thresholdvoltages of the reference cells can overlap the intervals associated tothe levels admissible for the array cells. In this case, systematicreading errors arise.

Even though the one-bit cells also suffer from the problem describedabove, said problem is much more serious in multilevel memories, becausethe levels are closer to one another and the margins narrow.

BRIEF SUMMARY OF THE INVENTION

One embodiment of the present invention provides a nonvolatile memorydevice and a control method thereof that are free from the drawbacksdescribed. One embodiment of the present invention, is directed to anonvolatile memory device that includes an array of memory cellsorganized in rows and columns, a first addressing circuit for addressingthe memory cells of the array on the basis of a cell address, and aplurality of sets of reference cells associated with the array. Each setof reference cells includes a plurality of reference cells. The memorydevice further comprises a second addressing circuit for addressing oneof the reference cells during operations of read and verify of addressedmemory cells.

One embodiment of the invention provides a control method for a memorydevice, the method comprising the steps of addressing memory cellsorganized in rows and columns in an array on the basis of a celladdress, associating a plurality of sets of reference cells with saidarray, and addressing one of said reference cells during read and verifyoperations of addressed memory cells.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

For a better understanding of the invention, some embodiments thereofare now described, purely by way of non-limiting example and withreference to the attached plate of drawings, wherein:

FIG. 1 shows a cross section through a nonvolatile memory cell of aknown type;

FIGS. 2 a-2 c are graphs that show the behavior of quantitiescorresponding to nonvolatile memory devices of a known type;

FIG. 3 is a simplified block diagram of a nonvolatile memory deviceaccording to a first embodiment of the present invention;

FIG. 4 is a more detailed block diagram of a part of the device of FIG.3;

FIG. 5 shows a simplified circuit diagram corresponding to one of theblocks of FIG. 4;

FIG. 6 is a logic diagram corresponding to a part of the device of FIG.3;

FIG. 7 is a simplified block diagram of a nonvolatile memory device madeaccording to a second embodiment of the present invention;

FIG. 8 is a more detailed block diagram of a part of the device of FIG.7;

FIG. 9 is a logic diagram corresponding to a part of the device of FIG.7; and

FIG. 10 is a simplified block diagram of a nonvolatile memory devicemade according to a third embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

With reference to FIG. 3, a nonvolatile memory device, designated as awhole by 10, comprises: an array 11 of memory cells 12, organized inrows and columns; a read/write (R/W) circuit 13; a row-decoder stage 14;a column-decoder stage 15; and a control unit 16. In one embodiment ofthe invention, the cells 12 are of the two-bit multilevel type (fourlevels). The row-decoder stage 14 and the column-decoder stage 15select, in ways in themselves known, one or more memory cells 12 forread and/or program operations, using a row address AWL and a columnaddress ABL, respectively, which form a cell address ADD supplied fromthe outside via an address bus (which is also known and not shown).

In order to render access to the memory cells 12 more flexible, thearray 11 is split into banks or partitions 17 independent with respectto one another (eight in the embodiment described herein). As shown inFIG. 4, a dedicated reference bank 19, an addressing stage 20, areference-selection circuit 21, and a sense circuit 18 are associated toeach of the partitions 17. While FIG. 4 shows one reference bank 19 andone partition 17, there are a plurality of reference banks associatedrespectively with the partitions 17 in one embodiment. For reasons ofsimplicity, in FIG. 4 and in the following description reference will bemade to just one sense circuit 18. It is, however, understood that eachpartition 17 can comprise more than one sense circuit 18 (for example128 sense circuits) in order to enable simultaneous access to as manymemory cells 12 for read or program operations in parallel.

Also the partitions 17 and the memory cells 12 are organized in rows andcolumns. In greater detail, memory cells 12 arranged on a same row areconnected to a same array wordline 22, and memory cells 12 arranged on asame column are connected to a same array bitline 23. The row-decoderstage 14 is configured for connecting selectively one of the arraywordlines 22 of the partition 17 to the R/W circuit 13. Likewise, thecolumn-decoder stage 15 is configured so as to connect selectively one(or a set) of the array bitlines 23 to the sense circuit 18.

As shown in FIG. 5, the reference bank 19 comprises a plurality of sets24 of reference cells organized in rows (for example 4, 8, 16 or 32). Inparticular, each set 24 of reference cells comprises three readreference cells 25 a, 25 b, 25 c (namely, one for each read referencelevel), three program-verify reference cells 26 a, 25 b, 26 c (namely,one for each program-verify level), one erase-verify reference cell 27and one depletion-verify reference cell 28. The number of read referencecells and program-verify reference cells indicated regards the exampledescribed herein, in which the memory cells 12 are of the four-leveltype; i.e., they are capable of storing two bits each. In general, inthe case of memory cells having M levels, each set of reference cellscomprises M−1 read reference cells and M−1 program-verify referencecells.

According to the embodiment described herein, in each set 24 ofreference cells, the read reference cells 25 a-25 c and theprogram-verify reference cells 26 a-26 c have their respective gateterminal connected to a same first reference wordline 30 and their drainterminal connected to respective reference bitlines 31. Furthermore, theerase-verify reference cell 27 and the depletion-verify reference cell28 of each set 24 of reference cells have their respective gateterminals connected to a same second reference wordline 32, separatedfrom the first reference wordline 30. The drain terminals of theerase-verify reference cell 27 and of the depletion-verify referencecell 28 are, instead, connected to respective bitlines 31. In oneembodiment (not illustrated), the reference cells of each set 24 ofreference cells all have their respective gate terminals connected to asame reference wordline.

The first and second reference wordlines 30, 32 of all the sets 24 ofreference cells are connected to the addressing stage 20, whereas thereference bitlines 31 are connected to the reference-selection stage 21.

With reference once again to FIG. 4, the reference-selection stage 21 iscontrolled by the control unit 16 by means of a selection signal S_(SEL)so as to connect one of the reference bitlines 31 to the sense circuit18, according to the type of operation to be carried out. For example,during a read step, the selection signal S_(SEL) operates on thereference-selection stage 21 such that the sense circuit 18 is coupledto the reference bitline 31 connected to one of the read reference cells25 a-25 c. Likewise, during a program-verify step, thereference-selection stage 21 couples the sense circuit 18 to the bitlineconnected to one of the program-verify reference cells 26 a-26 c.

The addressing stage 20 receives the column address ABL from the addressbus (not shown) and is configured for selectively connecting one of thefirst reference wordlines 30 or of the second reference wordlines 32 tothe R/W circuit 13 on the basis of the column address ABL (inparticular, using a number of address bits equal to log₂ N).

Consequently, the sense circuit 18 has a first sense terminal 18 a,addressably connectable to one of the array cells 12, and a second senseterminal 18 b, addressably connectable to one of the reference cells 25a-25 c, 26 a-26 c, 27, 28 of the reference bank 19. Once the first andsecond terminals 18 a, 18 b have been connected, under the guidance ofthe control unit 16 the sense circuit 18 reads or verifies the contentsof the memory cell 12 selected, according to the type of operation, andsupplies at output read data D₀.

In one embodiment, the selection is carried out as follows. The sets 24of reference cells are associated to respective sets S₀, S₁, . . . ,S_(N−1) of memory cells of the partition 17 of the array 11, defined bypredetermined groups of array bitlines 23 (N designates the number ofsets 24 of reference cells belonging to each of the reference banks 19).In one embodiment, each set S₀, S₁, . . . , S_(N−1) Of memory cellscomprises the memory cells of one array bitline 23 every N. As shown inFIG. 6 (where the array wordlines 22 are not illustrated, for reasons ofsimplicity), each partition 17 is hence logically split into N sets S₀,S₁, . . . , S_(N−1) Of memory cells, which are defined by array bitlines23 having column addresses ABL_(NK), ABL_(NK+1), . . . , ABL_(NK+N−1),respectively, with K=0, 1, . . . , (P/N)−1 (where P is the total numberof array bitlines 23 of each partition 17 and is an integer multiple ofN). For example, the set S₅ of memory cells comprises the memory cellsconnected to array bitlines 23 having column addresses ABL₅, ABL_(N+5),ABL_(2N+5), . . . , ABL_([(P/N)−1]+5). Once a memory cell 12 belongingto one of the sets S₀, S₁, . . . , S_(N−1) of memory cells is selected,the addressing stage 20 selects the first reference wordline 30 or thesecond reference wordline 32 of the corresponding set 24 of referencecells, according to the type of operation that must be performed (readoperation or program-verify operation in the first case, anderase-verify operation or depletion-verify operation in the secondcase).

The memory device described advantageously enables a reduction in theeffects of spurious programming of the reference cells. In fact, sinceeach partition 17 of the memory array 11 is provided with a plurality(N) of sets 24 of reference cells that are alternatively used in theread and verify operations, in practice, the average number of accessesto any one of the read reference cells 25 a-25 c, of the program-verifyreference cells 26 a-26 c, of the erase-verify reference cells 27 and ofthe depletion-verify reference cells 28 is reduced by N times. Theadverse effects of read disturb are reduced by the same amount.

Furthermore, the logic division of the partitions 17 into sets S₀, S₁, .. . , S_(N−1) of memory cells as described above allows optimizing ofthe alternation and renders use of the sets 24 of reference cellsuniform in the frequent case of page read/write (“burst mode”) of thememory cells 12. In this case, in fact, the memory cells 12 are accessedstarting from an initial address and incrementing the column address ABLby one unit at each cycle. Consequently, the sets 24 of reference cellsare selected cyclically in sequence. Thus, uneven use of the referencecells 25 a-25 c, 26 a-26 c, 27, 28 of the various sets 24 of referencecells is prevented.

Addressing of the reference cells 25 a-25 c, 26 a-26 c is based upon theuse of a portion of the address ADD of the memory cell 12 selected forthe read or verify operation to be carried out. In this way, associatedto each memory cell 12 is always a same set 24 of reference cells.

A further advantage of the memory device described derives from the useof separate reference wordlines for the read reference cells 25 a-25 cand program-verify reference cells 26 a-26 c on the one hand and for theerase-verify reference cells 27 and depletion-verify reference cells 28on the other. In this way, in fact, the erase-verify reference cells 27and the depletion-verify reference cells 28, which have lower thresholdvoltages and are more subject to read disturb, are more protected.

FIGS. 7-9, where parts that are the same as those already shown aredesignated by the same reference numbers previously used, shows anonvolatile memory device 100 made according to one embodiment of theinvention. The memory device 100 comprises an array 111 of memory cells12, split into partitions 117, the R/W circuit 13, the row-decoder stage14, the column-decoder stage 15, and the control unit 16.

A plurality of dedicated reference banks 19, having the structurealready described with reference to FIG. 5, are respectively associatedwith each partition 117 of the array 111 (FIG. 8). Furthermore, at leastone sense circuit 18, an addressing stage 120, and a reference-selectionstage 21 are associated to each of the partitions 117. Thereference-selection stage 21 and the sense circuit 18 are of the typesalready described and illustrated in FIG. 4. The addressing stage 120receives the row address AWL from the address bus (not shown) and isconfigured for connecting selectively one of the first referencewordlines 30 or of the second reference wordlines 32 of the referencebank 19 to the R/W circuit 13 on the basis of the row address AWL (inparticular, using a number of address bits equal to log₂ N).

As shown in FIG. 9 (where the array bitlines 23 are not illustrated, forreasons of simplicity), the sets 24 of reference cells are in this caseassociated to respective sets S₀′, S₁′, . . . , S_(N−1)′ of memory cellsof the partition 17 of the array 11, defined by predetermined groups ofarray wordlines 22 (N once again designates the number of sets 24 ofreference cells belonging to each of the reference banks 19). In oneembodiment, each set S₀′, S₁′, . . . , S_(N−1)′ of memory cellscomprises the memory cells of Q/N adjacent array wordlines 22, Q beingthe number of array wordlines 22 of each partition 117 (Q is an integermultiple of N). Consequently, each partition 17 is logically split intoN sets S₀′, S₁′, . . . , S_(N−1)′, Of memory cells which include thememory cells connected to array wordlines 22 having row addressesAWL_(K), AWL_((Q/N)+K), . . . , AWL_((N−1)(Q/N)+K), respectively, withK=0, 1, . . . , (Q/N)−1. Once a memory cell 12 belonging to one of thesets S₀′, S₁′, . . . , S_(N−1)′ of memory cells is selected, theaddressing stage 120 selects the first reference wordline 30 or thesecond reference wordline 32 of the corresponding set 24 of referencecells, according to the type of operation that must be performed (readoperation or program-verify operation in the first case, anderase-verify operation or depletion-verify operation in the secondcase).

With reference once again to FIGS. 7 and 8, the reference-selectionstage 21 is controlled by the control unit 16 by means of a selectionsignal S_(SEL) so as to connect one of the reference bitlines 31 to thesense circuit 18, according to the type of operation to be carried out,as already described with reference to FIG. 4.

Also in this case, the first terminal 18 a and the second terminal 18 bof the sense circuit 18 are addressably connectable to one of the arraycells 12 and to one of the reference cells 25 a-25 c, 26 a-26 c, 27, 28of the reference bank 19, respectively.

According to one embodiment of the invention, illustrated in FIG. 10, ina memory device 200 an array 211 of memory cells 12 is split intopartitions 217. A respective dedicated reference bank 19, having thestructure already described with reference to FIG. 5, at least one sensecircuit 18, an addressing stage 220, and a reference-selection stage 21are associated to each of the partitions 217. The addressing stage 220is driven by the control unit 16 by a control signal S_(C)for selectingone of the sets 24 of reference cells at each access to the partition217 of the array 211 according to a predetermined procedure. Forexample, the selection can occur in a sequential way or else by means ofa random-access algorithm.

Finally, it is clear that modifications and variations may be made tothe device and the method described herein, without departing from thescope of the present invention, as defined in the annexed claims.

1. A memory device comprising: an array of memory cells organized inrows and columns; a first addressing circuit for addressing said memorycells of said array on the basis of a cell address; a plurality of setsof reference cells associated with said array, each set of referencecells including a plurality of reference cells; and a second addressingcircuit for addressing one of said reference cells during operations ofread and verify of addressed memory cells.
 2. The device according toclaim 1, wherein the array comprises a plurality of partitions of saidmemory cells, wherein a respective plurality of said sets of referencecells is associated to each of said partitions.
 3. The device accordingto claim 2, comprising at least one sense circuit associated to saidpartition, said sense circuit having: a first sense terminal, configuredto be connected by address to one of said memory cells by said firstaddressing circuit; and a second sense terminal, configured to beconnected by address to one of said sets of reference cells by saidsecond addressing circuit.
 4. The device according to claim 2, whereinsaid second addressing circuit is configured for addressing saidreference cells on the basis of said cell address.
 5. The deviceaccording to claim 4, wherein said second addressing circuit isconfigured to address said reference cells on the basis of a columnportion of said cell address.
 6. The device according to claim 4,wherein said second addressing circuit is configured to address saidreference cells on the basis of a row portion of said cell address. 7.The device according to claim 2, wherein memory cells arranged on a samerow are connected to a same array wordline, and memory cells arranged ona same column are connected to a same array bitline, and wherein saidpartition is split into a plurality of sets of memory cells and the setsof reference cells associated to a partition are associated respectivelywith the sets of memory cells of that partition.
 8. The device accordingto claim 7, wherein each of said sets of memory cells comprises thememory cells connected to a plurality of said array bitlines.
 9. Thedevice according to claim 8, wherein each of said sets of memory cellscomprises the memory cells connected to one of said array bitlines everyN, where N is a number of said sets of reference cells associated withsaid partition.
 10. The device according to claim 7, wherein each ofsaid sets of memory cells comprises the memory cells connected to aplurality of said array wordlines.
 11. The device according to claim 10,wherein each of said sets of memory cells comprises the memory cellsconnected to Q/N adjacent said array wordlines, where N is a number ofsaid sets of reference cells associated with said partition and Q is thenumber of array wordlines associated with said partition.
 12. The deviceaccording to claim 1, wherein each of said sets of reference cellscomprises: at least one read reference cell; at least one program-verifyreference cell; an erase-verify reference cell; and a depletion-verifyreference cell.
 13. The device according to claim 12, wherein each ofsaid sets of reference cells, said at least one read reference cell,said at least one program-verify reference cell, said erase-verifyreference cell, and said depletion-verify reference cell are connectedto a same reference wordline.
 14. The device according to claim 12wherein in each set of reference cells, said read and program verifyreference cells are connected to a same first reference wordline, andsaid erase verify and depletion verify reference cells are connected toa same second reference wordline.
 15. The device according to claim 1,wherein said memory cells are multilevel nonvolatile memory cells.
 16. Acontrol method for a memory device, the method comprising the steps of:addressing memory cells organized in rows and columns in an array on thebasis of a cell address; associating a plurality of sets of referencecells, each comprising a plurality of reference cells, with said array;and addressing one of said reference cells during read and verifyoperations of addressed memory cells.
 17. The method according to claim16, comprising the step of associating at least one sense circuit tosaid array, and wherein said step of addressing memory cells comprisesaddressably connecting a first sense terminal of said sense circuit toone of said memory cells, and said step of addressing one of saidreference cells comprises addressably connecting a second sense terminalof said sense circuit to one of said sets of reference cells.
 18. Themethod according to claim 16, wherein said step of addressing one ofsaid reference cells comprises using said cell address.
 19. The methodaccording to claim 18, wherein said step of addressing one of saidreference cells comprises using a column portion of said cell address.20. The method according to claim 18, wherein said step of addressingone of said reference cells comprises using a row portion of said celladdress.
 21. The method according to claim 16, wherein memory cellsarranged on a same row are connected to a same array wordline, andmemory cells arranged on a same column are connected to a same arraybitline, the method comprising the steps of: splitting said array into aplurality of sets of memory cells; and associating said sets ofreference cells respectively with the sets of memory cells.
 22. Themethod according to claim 21, wherein each of said sets of memory cellscomprises the memory cells connected to a plurality of said arraybitlines.
 23. The method according to claim 22, wherein each of saidsets of memory cells comprises the memory cells connected to one of saidarray bitlines every N, where N is a number of said sets of referencecells associated to said array.
 24. The method according to claim 21,wherein each of said sets of memory cells comprises the memory cellsconnected to a plurality of said array wordlines.
 25. The methodaccording to claim 24, wherein each of said sets of memory cellscomprises the memory cells connected to Q/N adjacent said arraywordlines, where N is a number of said sets of reference cellsassociated to said array and Q is the number of array wordlines in thearray.
 26. The method according to claim 16, wherein each of said setsof reference cells comprises: at least one read reference cell; at leastone program-verify reference cell; an erase-verify reference cell; andand a depletion-verify reference cell.
 27. A control method for a memorydevice, the memory device having an array of memory cells arranged inrows and columns and being organized into a plurality of partitions ofmemory cells arranged in rows and columns, the method comprising:associating a plurality of banks of reference cells respectively withthe plurality of partitions, each bank of reference cells having aplurality of sets of reference cells; and addressing a reference cellfrom one of the sets of reference cells during a read or verifyoperation of a memory cell of the partition with which the sets ofreference cells are associated.
 28. The method according to claim 27comprising associating each set of reference cells with a respective setof memory cells of the partition such that a reference cell of one ofthe sets of reference cells is addressed during operations of read orverify of a memory cell of a set of memory cells associated with thatset of reference cells.
 29. The method according to claim 28 whereineach set of memory cells comprises one or more columns of memory cellsin a partition.
 30. The method according to claim 29 wherein each set ofmemory cells comprises a column every N columns in a partition, where Nis the number of sets of reference cells associated to the partition.31. The method according to claim 28 wherein each set of memory cellscomprises one or more rows of memory cells in a partition.
 32. Themethod according to claim 31 wherein each set of memory cells comprisesa plurality of adjacent rows in a partition.
 33. The method according toclaim 27 wherein the reference cell being addressed is addressedaccording to a procedure comprising a random access algorithm.
 34. Themethod according to claim 27 wherein the reference cell being addressedis addressed according to a procedure comprising a sequential selectionpattern.
 35. The method according to claim 27 wherein each set ofreference cells comprises: one or more read reference cells; one or moreprogram-verify reference cells; an erase-verify reference cell; and adepletion-verify reference cell.
 36. The method according to claim 35wherein the number of read reference cells and the number ofprogram-verify reference cells in each set of reference cells are oneless than the number of levels in a memory cell associated with that setof reference cells.
 37. A memory device comprising: a plurality ofmemory cells arranged in an array of rows and columns and organized intoa plurality of partitions of memory cells arranged in rows and columns;a plurality of banks of reference cells, the banks being respectivelyassociated with the plurality of partitions, each bank having aplurality of sets of reference cells; an addressing circuit configuredto address a reference cell from one of the sets of reference cellsduring read or verify operations of a memory cell of a partitionassociated with that set of reference cells.
 38. The device according toclaim 37 wherein the sets of reference cells are associated respectivelywith sets of memory cells of the partition.
 39. The device according toclaim 38 wherein each set of memory cells comprises one or more columnsof memory cells of the partition.
 40. The device according to claim 39wherein each set of memory cells comprises a column every N columns in apartition, where N is the number of sets of reference cells associatedto the partition.
 41. The device according to claim 38 wherein each setof memory cells comprises one or more rows of memory cells of apartition.
 42. The device according to claim 39 wherein each set ofmemory cells comprises a plurality of adjacent rows in a partition,where N is the number of sets of reference cells associated to thatpartition.
 43. The device according to claim 37 wherein the addressingcircuit is configured to address a reference cell of a set of referencecells according to a random access algorithm.
 44. The device accordingto claim 37 wherein the addressing circuit is configured to address areference cell of a set of reference cells according to a sequentialpattern.
 45. The device according to claim 37 wherein each set ofreference cells comprises: one or more read reference cells; one or moreprogram-verify reference cells; an erase-verify reference cell; and adepletion-verify reference cell.